1. Field of the Invention
The present invention relates to an apparatus for analyzing a substrate employing a copper decoration. More particularly, the present invention relates to an apparatus for analyzing a substrate employing a copper decoration for analyzing a crystalline defect existing in a silicon wafer.
2. Description of the Related Art
As semiconductor devices become more highly integrated, the quality of silicon wafers used as substrates for the semiconductor devices has a greater effect on manufacturing yield of the semiconductor devices and reliability of the semiconductor devices. The quality of a silicon wafer may be determined by a distribution and density of defects generated in the silicon wafer and on a surface of the silicon wafer during a process for manufacturing the silicon wafer.
Generally, in silicon wafer manufacturing technology, after a poly-crystalline silicon ingot is provided, a single crystalline silicon ingot is manufactured using a Czochoralski crystal growth process or a float zone crystal growth process. The single crystalline silicon ingot is cut to form a thin silicon wafer. After one face of the thin silicon wafer is polished, the polished silicon wafer is cleaned to complete the silicon wafer for the semiconductor devices.
When the silicon wafer is manufactured employing the above-described method, crystalline defects such as D-defects, crystal original particles (COP) and oxygen extractions are frequently generated on the silicon wafer or in the silicon wafer. When an oxide film is formed on the silicon wafer having the crystalline defects, the oxide film may have a poor characteristic at portions of the silicon wafer where the crystalline defects are generated. Particularly, the crystalline defects may cause failures of a gate oxide film and a shallow trench isolation (STI) of a semiconductor device.
To prevent the above-mentioned failures, a method for rapidly and precisely analyzing defects generated in or on the silicon wafer is important. Methods for analyzing defects of a silicon wafer include a method for analyzing a silicon wafer using a particle measurement apparatus, a method for analyzing a silicon wafer using an etching apparatus, a method for analyzing a silicon wafer using a laser scattering particle counter, and a method for analyzing a silicon wafer employing a destruction of an oxide film through manufacturing a metal oxide semiconductor (MOS) device. However, each of these methods may have respective disadvantages. In particular, with the method using the particle measurement apparatus, only defects having very small dimensions, of below about 0.12 μm, can be found at a portion of a silicon wafer. Although defects generated in the silicon wafer may be measured by the methods using the etching apparatus and the laser scattering particle counter, original shapes of the defects may be destructed by using these methods. Additionally, although defects generated in a silicon wafer may be analyzed by an effect thereof to an oxide film in the method employing the destruction of the oxide film through manufacturing a MOS device, it is very difficult to analyze morphologies of the defects by this method.
Recently, a copper decoration method for analyzing defects of a silicon wafer has been developed in an effort to overcome the above-mentioned problems. In the copper decoration method, after a silicon oxide film is formed on a silicon wafer, an electric field is applied to both ends of the silicon wafer so that copper ions are adsorbed at portions of the silicon wafer where defects are generated.
FIG. 1 illustrates a schematic cross-sectional view of a conventional copper decoration apparatus for analyzing a substrate.
Referring to FIG. 1, a conventional copper decoration apparatus 10 has a bath 14, a lower copper plate 16, an upper copper plate 18 and a power source 20.
The bath receives an electrolyte 12. The lower copper plate 16 is placed on a bottom face of the bath 14. A rear face of a silicon wafer W to be analyzed is placed on the lower copper plate 16. The upper copper plate 18 corresponds to the lower copper plate 16, and is separated from the lower copper plate 16. The power source 20 applies voltages to the upper and lower copper plates 16 and 18.
With the above-described conventional apparatus 10, one silicon wafer W is analyzed through one process for analyzing a defect of the silicon wafer W. Including preparatory processes for analysis, about one hour is required to analyze one silicon wafer W. Thus, the time required for analyzing several silicon wafers may be greatly increased when a plurality of silicon wafers are analyzed using the conventional copper decoration apparatus 10. Also, a method for analyzing silicon wafers may be complicated because each wafer should undergo several hours worth of preparatory processes prior to being analyzed.